Speaker 0:  we spent decades cramming more transistors onto flat silicon, but humanity just hit a hard atomic wall. now a massive breakthrough from the university of illinois has officially taken microchips into the third dimension, and it's about to supercharge ai. microchips are going sky high, so research has just figured out how to build layers of high performance single crystal silicon circuits directly on top of one another with near perfect manufacturing yields by using ultrathin 10 nanometer membranes and low temperature bonding, then bypass the extreme heat that used to melt the lower layers, during the production. so this blows the lid off our current computing bottlenecks paving the way for specialized hardware that could eventually run up to a thousand times more efficiently than anything we have today. what do you think about this, john?

Speaker 1:  yeah. as i was reading through this, i i just thought maybe we covered this before, but maybe not. but so, because we've covered so many topics, and i know we've covered three d chips before, but i don't know if we've covered this specifically. but, anyways, let's let's get everyone on the same page. so let's talk about why moore's law is slowing down. so moore's law originally described the observation that transistor density doubles roughly over two years. and so this trend, it fueled decades of exponential computing improvements. however, modern chips are approaching physical limits where quantum effects, heat generation, leakage current, and manufacturing complexity become major obstacles. today's leading edge chips contain transistors measured in just a few nanometers. at these scales, electron tunneling becomes problematic, power density rises, manufacturing costs explode, and yield rates become harder to maintain. so the breakthrough here is this illinois team has developed a method called sequential silicon stacking. so unlike traditional packaging approaches where separate chips are manufactured then assembled together, this technique, which is crazy, it directly builds multiple layers of high performance silicon electronics sequentially on the exact same wafer. and so this innovation, like you said, it involves ultra thin silicon membranes, low temperature fabrication processes, layer by layer circuit integration, and direct monolithic three d construction, which allows for multiple transistor layers to coexist without damaging previously fabricated circuitry. so historically, the temperature required to manufacture upper layers would destroy the lower layers. and so this new process, this overcomes that. this is a game changer. and i'm excited for this. what are your thoughts? do you think is, this is what's gonna save us from moore's law, craig?

Speaker 0:  well, we talked about a bunch of things, you know, around, low power, ai, and we've talked about, stacking for more power now. and we have talked about three d chips, but they and we talked about carbon nanotube building on them. but i think this is the first time we've talked about you know, they've got this layer in between that prevents the melting and the heat transposition. industry analysts expect commercial pilot, manufacturing to kick off within three to five years, so in 2029 to 2031. and we figured that it's it will debut in massive data centers, and specialized cloud ai accelerators before we might see anything at the consumer level. but think of this as update like city planning. for sixty years, we've been expanding our tech city via urban sprawl, spreading transistors out flat across a single piece of land. but now we've run out of room and traffic between the houses hitting our crawl. so this breakthrough lets us stop building suburbs and start building skyscrapers. we're putting the exact same high quality infrastructure on multiple floors with, lightning fast express elevators connecting them. deeply integrating the next generation micro tech, architecture roadmaps of the heavy hitters like intel, tsmc, and ibm. so this is already in their plans. so i'm gonna say, yes. this will be the next generation. you won't be buying a three d chip tomorrow, but this tech will soon prevent the ai models you use from lagging daily or costing a fortune to run. so we'll see how that goes.

Speaker 1:  yeah. this is cool. so the benefits of this, for those of you that don't know, are lower latency, reduced power consumption, higher transistor density, faster memory access, and greater ai processing efficiency. all things that are pretty simple, but makes sense that this would, alleviate that. because conventional chips, typical memory would sit far away from compute units, and so singles have to travel long distance. and so energy is wasted moving this information. so if if they can if they can mass produce this, if they can get to a point, this is awesome. and this matters more than another small chip because most people think chip innovation means five nanometer, three nanometer, two nanometer, whatever. but shrinking transistors alone is becoming inefficient. so this changes the breakthrough from how small can we go to how intelligently can we organize computation. so that's what i like about this.

Speaker 0:  so the team utilized junctionless transistors where the ultra thin silicon membranes are heavily and uniformly, doped before transfer. because the films are so minuscule, the transistor gates maintain absolute electrostatic control over the current without requiring the destructive 600 degree celsius plus thermal steps usually needed to create distinct source drain junctions. so this is the most profound architectural paradigm shift since the commercialization of finfet three d tri gate transistors in 2011. instead of simply changing the shape of the gate on a flat plane, we are functionally altering the physical coordinate space of the silicon layer. so the paper detailing this microelectronics breakthrough was published in nature, a journal that rarely accepts mainstream silicon hardware papers unless the physics completely upends the status quo. the research wasn't hidden away, and an ivory tower was funded via the silicon crosswords microelectronic coms commons hub, an ecosystem directly bankrolled by the us chips and science act. and to get the layers perfectly flushed, the researchers used a specialized mechanical roll laminator. the state of the art process looks surprisingly like a ultra high-tech version of putting a screen protector on a smartphone without tap trapping any air bubbles. yeah. so while the 98, to a 100% transition yield is stunning for research lab doing this on a three layer stack on 1,875 devices is vastly different from doing it across billions of transistors on a commercial 300 millimeter wafer. true mass production scalability and long term heat dissipation. within the center of a dense three d stack remains unproven. so any last words on this, john?

Speaker 1:  no. i'm excited for this.

Speaker 0:  yeah. moore's law isn't dead. it has just changed, dimensions to survive. if technology actually scales up and drops computing power cost to near zero, what is the first thing you want ai to solve? let us know in the chat.